/*----------------------------------------------------------------------------
 * Copyright (c) <2013-2015>, <Huawei Technologies Co., Ltd>
 * All rights reserved.
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 * 1. Redistributions of source code must retain the above copyright notice, this list of
 * conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright notice, this list
 * of conditions and the following disclaimer in the documentation and/or other materials
 * provided with the distribution.
 * 3. Neither the name of the copyright holder nor the names of its contributors may be used
 * to endorse or promote products derived from this software without specific prior written
 * permission.
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *---------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
 * Notice of Export Control Law
 * ===============================================
 * Huawei LiteOS may be subject to applicable export control laws and regulations, which might
 * include those applicable to Huawei LiteOS of U.S. and the country in which you are located.
 * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such
 * applicable export control laws and regulations.
 *---------------------------------------------------------------------------*/
#include "stdio.h"
#include "stdlib.h"
#include "los_atomic.h"
#include "hisoc/usb3.h"
#include "asm/hal_platform_ints.h"

extern VOID LOS_Mdelay(UINT32 msecs);

#define USB3_CTRL   IO_ADDRESS(CRG_REG_BASE + 0xB8)
#define USB3_VCC_SRST_REQ   (0x01U << 0)
#define USB3_COMBPHY    IO_ADDRESS(CRG_REG_BASE + 0xAC)
#define HI3519_COMBPHY_SRST_REQ (0x01U << 0)
#define REG_GUSB3PIPECTL0   IO_ADDRESS(CONFIG_HIUSB_XHCI_IOBASE + 0xc2c0)
#define PCS_SSP_SOFT_RESET      (0x1U << 31)
#define REG_GUSB2PHYCFG0    IO_ADDRESS(CONFIG_HIUSB_XHCI_IOBASE + 0xC200)
#define BIT_UTMI_ULPI         (0x1U << 4)
#define BIT_UTMI_8_16         (0x1U << 3)
#define GTXTHRCFG   IO_ADDRESS(CONFIG_HIUSB_XHCI_IOBASE + 0xc108)
#define GRXTHRCFG   IO_ADDRESS(CONFIG_HIUSB_XHCI_IOBASE + 0xc10c)
#define REG_GCTL    IO_ADDRESS(CONFIG_HIUSB_XHCI_IOBASE + 0xc110)

#define USB3_PERI_CRG45   IO_ADDRESS(CRG_REG_BASE + 0xB4)
#define USB3_PERI_CRG46   IO_ADDRESS(CRG_REG_BASE + 0xB8)
#define USB3_PERI_CRG43   IO_ADDRESS(CRG_REG_BASE + 0xAC)
#define MISC_CTRL1  IO_ADDRESS(MISC_REG_BASE + 0x0004)

static int dev_open_cnt = 0;
static int otg_usbdev_stat = 0;

void hiusb3_host2device(void)
{
    unsigned int reg;

    reg = GET_UINT32(REG_GCTL);
    reg &= ~(0x3<<12);
    reg |= (0x1<<13); /*[13:12] 01: Host; 10: Device; 11: OTG*/
    WRITE_UINT32(reg, REG_GCTL);
    LOS_Udelay(20);
}

static int hisi_usb3_phy_config(void)
{
    unsigned int reg;

    reg = GET_UINT32(REG_GUSB3PIPECTL0);
    reg |= PCS_SSP_SOFT_RESET;
    WRITE_UINT32(reg, REG_GUSB3PIPECTL0);

    reg = GET_UINT32(REG_GUSB2PHYCFG0);
    reg &= ~BIT_UTMI_ULPI;
    reg &= ~(BIT_UTMI_8_16);
    WRITE_UINT32(reg, REG_GUSB2PHYCFG0);
    LOS_Mdelay(20);

    reg = GET_UINT32(REG_GCTL);
    reg &= ~(0x3<<12);
    reg |= (0x1<<12); /*[13:12] 01: Host; 10: Device; 11: OTG*/
    WRITE_UINT32(reg, REG_GCTL);
    LOS_Mdelay(20);

    reg = GET_UINT32(REG_GUSB3PIPECTL0);
    reg &= ~PCS_SSP_SOFT_RESET;
    reg &= ~(1<<17);       /* disable suspend */
    WRITE_UINT32(reg, REG_GUSB3PIPECTL0);
    LOS_Mdelay(100);

    WRITE_UINT32(0x0, IO_ADDRESS(0x120401ac));
    LOS_Mdelay(20);
    WRITE_UINT32(0x8, IO_ADDRESS(0x1214d400));
    LOS_Mdelay(20);
    WRITE_UINT32(0x8, IO_ADDRESS(0x1214d020));
    LOS_Mdelay(200);
    WRITE_UINT32(0x23100000, GTXTHRCFG);
    WRITE_UINT32(0x23100000, GRXTHRCFG);
    LOS_Mdelay(20);

    reg = GET_UINT32(MISC_CTRL1);
    reg |= 0x01 << 15;
    WRITE_UINT32(reg, MISC_CTRL1);
    LOS_Mdelay(10);

    return 0;
}

static int hisi_usb3_phy_power_off(void)
{
    unsigned int reg;
    if (LOS_AtomicDecRet(&dev_open_cnt) == 0) {
        reg = GET_UINT32(USB3_COMBPHY);
        reg |=  HI3519_COMBPHY_SRST_REQ;
        WRITE_UINT32(reg, USB3_COMBPHY);
        LOS_Msleep(100);

        reg = GET_UINT32(USB3_CTRL);
        reg |=  USB3_VCC_SRST_REQ;
        WRITE_UINT32(reg, USB3_CTRL);
        LOS_Mdelay(10);
    }
    return 0;
}

static int hisi_usb3_phy_power_on(void)
{
    unsigned int reg;

    if (LOS_AtomicIncRet(&dev_open_cnt) == 1) {
        reg = GET_UINT32(USB3_PERI_CRG45);
        reg = 0xf9;
        /*Revoke U2PHY reset*/
        WRITE_UINT32(reg, USB3_PERI_CRG45);
        LOS_Mdelay(10);

        reg = GET_UINT32(USB3_PERI_CRG46);
        reg = 0x1f01;
        /*U3 controller UTMI clock source selection U2PHY supply*/
        WRITE_UINT32(reg, USB3_PERI_CRG46);
        LOS_Mdelay(10);

        reg = GET_UINT32(USB3_PERI_CRG43);
        reg |= 0x01 << 9;
        /*Select COMPHYPHY reference clock 25M*/
        WRITE_UINT32(reg, USB3_PERI_CRG43);
        LOS_Mdelay(10);

        reg = GET_UINT32(USB3_PERI_CRG43);
        reg |= 0x01 << 8;
        /*Select COMPHY clock gating*/
        WRITE_UINT32(reg, USB3_PERI_CRG43);
        LOS_Mdelay(10);

        reg = GET_UINT32(USB3_PERI_CRG43);
        reg |= 0x01 << 1;
        /*COMPHY port soft reset mode selection is controlled by PERI_CRG45 [0]*/
        WRITE_UINT32(reg, USB3_PERI_CRG43);
        LOS_Mdelay(10);

        reg = GET_UINT32(USB3_PERI_CRG43);
        reg &= ~(0x01);
        /*Revoke COMPHY reset*/
        WRITE_UINT32(reg, USB3_PERI_CRG43);
        LOS_Mdelay(10);

        reg = GET_UINT32(USB3_PERI_CRG46);
        reg &= ~(0x01);
        /*Revoke U3 controller reset*/
        WRITE_UINT32(reg, USB3_PERI_CRG46);
        LOS_Mdelay(10);

        (void)hisi_usb3_phy_config();
    }
    return 0;
}

void hiusb3_start_hcd(void)
{
    (void)hisi_usb3_phy_power_on();
}
void hiusb3_stop_hcd(void)
{
    (void)hisi_usb3_phy_power_off();
}

void hiusb3_reset_hcd(void)
{
}

int hiusb_is_device_mode(void)
{
    return (otg_usbdev_stat == 1);
}

void usb_otg_sw_set_device_state(void)
{
    otg_usbdev_stat = 1;
}

void usb_otg_sw_clear_device_state(void)
{
    otg_usbdev_stat = 0;
}


